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 STSJ25NF3LL
N-CHANNEL 30V - 0.0085 - 25A PowerSO-8TM LOW GATE CHARGE STripFETTM II POWER MOSFET
TYPE STSJ25NF3LL
s s s s s
VDSS 30 V
RDS(on) <0.0105
ID 25 A
TYPICAL RDS(on) = 0.0085 @ 10V TYPICAL Qg = 24 nC @ 4.5 V CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED IMPROVED JUNCTION-CASE THERMAL RESISTANCE PowerSO-8TM
DESCRIPTION This Power MOSFET is the latest development of STMicroelectronics unique "Single Feature SizeTM" strip-based process. This silicon, housed in thermally improved SO-8TM package, exhibits optimal on-resistance versus gate charge tradeoff plus lower R thj-c.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS s SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS FOR MOBILE PCS DRAIN CONTACT ALSO ON THE BACKSIDE
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VDGR VGS ID ID ID IDM(*) Ptot Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C (*) Drain Current (continuous) at TC = 25C (#) Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Total Dissipation at TC = 25C (#) Value 30 30 16 25 12 16 100 70 3
(*) Value limited by wires bonding
Unit V V V A A A A W W
(*) Pulse width limited by safe operating area. October 2003
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NEW DATASHEET ACCORDING TO PCN DSG/CT/2C13 MARKING: 25NF3LL@
STSJ25NF3LL
THERMAL DATA
Rthj-c Rthj-amb Tj Tstg Thermal Resistance Junction-case (*)Thermal Resistance Junction-ambient Maximum Operating Junction Temperature Storage Temperature Max Max 1.8 42 150 -55 to 150 C/W C/W C C
(*) When mounted on FR-4 board with 0.5 in2 pad of Cu.
ELECTRICAL CHARACTERISTICS (Tcase = 25 C unless otherwise specified) OFF
Symbol V(BR)DSS IDSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating TC = 125C VGS = 16 V Min. 30 1 10 100 Typ. Max. Unit V A A nA
IGSS
ON (*)
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V VGS = 4.5 V ID = 250 A ID = 12.5 A ID = 12.5 A Min. 1 0.0085 0.011 0.0105 0.013 Typ. Max. Unit V
DYNAMIC
Symbol gfs (*) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS=15 V ID = 12.5 A Min. Typ. 20 1650 540 130 Max. Unit S pF pF pF
VDS = 25V, f = 1 MHz, VGS = 0
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STSJ25NF3LL
ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions ID = 12.5 A VDD = 15 V RG = 4.7 VGS = 4.5 V (Resistive Load, Figure 1) VDD=15V ID=25A VGS=4.5V
(see test circuit, Figure 2)
Min.
Typ. 23 156 24 8.5 12
Max.
Unit ns ns
33
nC nC nC
SWITCHING OFF
Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions ID = 12.5 A VDD = 15 V RG = 4.7, VGS = 4.5 V (Resistive Load, Figure 3) Min. Typ. 27 28 Max. Unit ns ns
SOURCE DRAIN DIODE
Symbol ISD ISDM (*) VSD (*) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 25 A VGS = 0 40 50 2.5 Test Conditions Min. Typ. Max. 25 100 1.2 Unit A A V ns nC A
di/dt = 100A/s ISD = 25 A VDD = 25 V Tj = 150C (see test circuit, Figure 3)
(*)Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (*)Pulse width limited by safe operating area.
Safe Operating Area
Thermal Impedance
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STSJ25NF3LL
Output Characteristics Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
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STSJ25NF3LL
Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics
Normalized Breakdown Voltage vs Temperature.
.
.
5/8
STSJ25NF3LL
Fig. 1: Switching Times Test Circuits For Resistive Load Fig. 2: Gate Charge test Circuit
Fig. 3: Test Circuit For Diode Recovery Behaviour
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STSJ25NF3LL
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STSJ25NF3LL
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (R) 2003 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco -Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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